BlockWare Library
The BlockWare Library represents a comprehensive collection of parameterized library designed to revolutionize ASIC design workflows. Each component is meticulously crafted to provide superior performance, enhanced flexibility, and seamless integration into your design environment. Our library enables direct physical netlist generation from RTL, ensuring complete consistency between frontend and backend implementation.
Arbiter and Wavefront
| Component | Description |
|---|---|
| Dynamic Priority Arbiter | Arbiter with dynamically adjustable priority levels for flexible resource allocation |
| First-Come-First-Served Arbiter | FIFO-based arbiter ensuring fair sequential access to shared resources |
| Round Robin Arbiter | Circular scheduling arbiter providing equal access opportunities to all requesters |
| Static Priority Arbiter | Fixed priority arbiter for deterministic resource allocation based on predefined hierarchy |
| Wavefront Arbiter | Advanced arbiter using wavefront scheduling algorithm for optimal throughput |
| Weight Round Robin Arbiter | Weighted round-robin scheduler for proportional bandwidth allocation based on configurable weights |
Arithmetic Logic
| Component | Description |
|---|---|
| abs subtractor | Absolute value subtractor for signed arithmetic operations |
| absvalue | Absolute value calculator for signed number processing |
| add or sub | Dual-function arithmetic unit performing addition or subtraction based on control signal |
| adder | Parameterized adder with configurable width and optimization strategies |
| bin2gray | Binary to Gray code converter for glitch-free counting |
| carry save adder | Carry-save adder for efficient multi-operand addition |
| comparator2 | 2-input comparator for equality, greater-than, and less-than operations |
| comparator6 | 6-input parallel comparator for complex comparison operations |
| compound add or sub | Compound add/subtract unit for complex arithmetic operations |
| compound adder | Compound adder for multi-operand addition operations |
| compound subtractor | Compound subtractor for multi-operand subtraction operations |
| decrementer | High-speed decrementer for countdown operations and loop control |
| dot products | Vector dot product calculator for signal processing and AI acceleration |
| gray2bin | Gray code to binary converter for asynchronous interface applications |
| gray incrementer | Gray code incrementer for glitch-free counting applications |
| gray incrementer decrementor | Bidirectional Gray code counter for up/down counting |
| inc dec | Combined incrementer/decrementer unit for flexible counting |
| incrementer | Optimized incrementer circuit for counter and address generation applications |
| integer squarer | Dedicated squaring unit optimized for power and area efficiency |
| integer squarer partial product | Integer squarer using partial product method for enhanced performance |
| multiplier | High-performance multiplier with multiple pipeline stage options |
| multiplier 2 stages | Two-stage pipelined multiplier for balanced latency and throughput |
| multiplier 3 stages | Three-stage pipelined multiplier for maximum throughput |
| multiplier accumlater | Multiply-accumulate unit for DSP and machine learning applications |
| multiplier adder fma | Fused multiply-add unit for enhanced precision and performance |
| satrnd | Saturation and rounding unit for fixed-point arithmetic |
| subtractor | Optimized subtractor module supporting various arithmetic operations |
| vector adder | Vector addition unit for parallel arithmetic operations |
| vector adder compressor | Vector adder with compression for efficient multi-operand addition |
| wallace tree | Wallace tree multiplier architecture for high-speed multiplication |
Combinational Logic
| Component | Description |
|---|---|
| andgate | Parameterized AND gate with configurable input width and drive strength |
| count ones | Population count (popcount) circuit for counting set bits |
| decoder | Binary to one-hot decoder for address decoding and control logic |
| decoder with en | Decoder with enable signal for conditional decoding operations |
| encoder | Priority encoder converting one-hot signals to binary representation |
| leading one detector | Leading one detector for bit scanning and priority resolution |
| leading sign detector | Leading sign bit detector for signed number normalization |
| leading zero anticipator | Anticipates leading zeros for fast normalization in arithmetic operations |
| leading zero detector | Leading zero detection for normalization and floating-point operations |
| move ones left | Shifts all set bits to the left positions in a vector |
| move ones right | Shifts all set bits to the right positions in a vector |
| mux 1bit | Single-bit multiplexer with parameterized select width |
| mux vec | Vector multiplexer for multi-bit data path selection |
| nandgate | NAND gate implementation with multiple optimization modes |
| norgate | NOR gate with configurable input count for logic synthesis |
| orgate | Scalable OR gate for wide fan-in logical operations |
| priority encoder | Advanced priority encoder with configurable priority direction |
| priority selector left | Priority selector with left-to-right precedence for arbitration |
| priority selector right | Priority selector with right-to-left precedence for arbitration |
| residues3 | Modulo-3 residue calculator for RNS arithmetic systems |
| thermometer decoder with en | Thermometer decoder with enable for ADC and priority encoding applications |
| xnorgate | XNOR gate for equivalence checking and error detection |
| xorgate | XOR gate optimized for parity generation and comparison circuits |
Clock Domain Crossing
| Component | Description |
|---|---|
| Data Bus Synchronizer with Acknowledge | Multi-bit data synchronizer with handshake acknowledgment for reliable cross-domain transfer |
| Data Bus Synchronizer without Acknowledge | Simple multi-bit data synchronizer for clock domain crossing without handshake |
| Dual Clock Pulse Synchronizer | Pulse synchronizer for transferring single-cycle signals across clock domains |
| Single Clock Data Bus Synchronizer | Data bus synchronizer for single clock domain with pipeline stages |
Counters
| Component | Description |
|---|---|
| counter | Basic parameterized counter with configurable width and direction |
| counter gray load | Gray code counter with load for glitch-free asynchronous applications |
| counter gray updn load | Bidirectional Gray code counter with load capability |
| counter lfsr | Linear feedback shift register counter for pseudo-random sequence generation |
| counter lfsr load | LFSR counter with load capability for seed initialization |
| counter lfsr updn | Bidirectional LFSR counter for reversible pseudo-random sequences |
| counter lfsr updn load | Bidirectional LFSR counter with load for flexible seed control |
| counter lfsr updn with dynamic flag | Bidirectional LFSR counter with runtime-configurable terminal detection |
| counter lfsr updn with static flag | Bidirectional LFSR counter with compile-time terminal count |
| counter lfsr with dynamic flag | LFSR counter with runtime-configurable terminal count detection |
| counter lfsr with static flag | LFSR counter with fixed terminal count for optimized area |
| counter load | Counter with parallel load capability for preset values |
| counter updn | Bidirectional counter supporting both up and down counting modes |
| counter updn load | Up/down counter with load functionality for flexible initialization |
| counter updn load decode | Up/down counter with load and decode logic for state detection |
| counter updn with dynamic flag | Bidirectional counter with programmable limit detection |
| counter updn with dynamic flag min power | Power-optimized bidirectional counter with programmable limit |
| counter updn with static flag | Bidirectional counter with fixed terminal count for area optimization |
| counter updn with static flag min power | Power-optimized bidirectional counter with fixed terminal count |
| counter with dynamic flag | Counter with runtime-configurable terminal count detection |
| counter with static flag | Counter with compile-time fixed terminal count for optimized area |
Data Integrity
| Component | Description |
|---|---|
| ecc | Error correction code module with single-error correction and double-error detection (SECDED) |
| ecc gen | ECC syndrome generation for memory and communication error protection |
| parity generator and checker | Configurable parity generation and checking for simple error detection |
Data Integrity Coding
| Component | Description |
|---|---|
| 8b10b encoder | 8b/10b encoder for DC-balanced serial communication with embedded clock |
| 8b10b decoder | 8b/10b decoder with disparity checking and special character detection |
| 8b10b coding balance predictor | Disparity prediction module for 8b/10b encoding optimization |
Digital Signal Processing
| Component | Description |
|---|---|
| FIR | Finite Impulse Response filter with configurable taps and coefficients |
| IIR | Infinite Impulse Response filter with feedback structure for recursive filtering |
Floating Point
| Component | Description |
|---|---|
| floating point adder | IEEE 754 compliant floating-point adder with normalization and rounding |
| floating point subtractor | Floating-point subtractor with exception handling (NaN, infinity, underflow) |
| floating point adder subtractor | Unified floating-point add/subtract unit for area optimization |
| floating point multiplier | High-precision floating-point multiplier with configurable pipeline stages |
| floating point multiply and add | Fused multiply-add (FMA) unit for enhanced accuracy and performance |
| floating point comparator | Floating-point comparison with special value handling |
| integer2floating point converter | Integer to floating-point format converter with rounding modes |
| floating point2integer converter | Floating-point to integer converter with saturation and truncation options |
Memory FIFO
| Component | Description |
|---|---|
| asymmetric fifo with dynamic flags | Asymmetric FIFO with runtime-configurable full/empty thresholds for flexible buffering |
| asymmetric fifo with static flags | Asymmetric FIFO with compile-time fixed flags for optimized area |
| dual clock asymmetric fifo with dynamic flags | Dual-clock asymmetric FIFO with programmable flags for cross-domain data transfer |
| dual clock asymmetric fifo with static flags | Dual-clock asymmetric FIFO with fixed threshold flags for CDC applications |
| dual clock fifo with dynamic flags | Dual-clock FIFO with runtime-configurable status flags for asynchronous buffering |
| dual clock fifo with static flags | Dual-clock FIFO with fixed flags for simple cross-domain data transfer |
| dual clock multi req fifo with dynamic flags | Dual-clock multi-request FIFO with programmable flags for burst transfers |
| dual clock multi req fifo with static flags | Dual-clock multi-request FIFO with fixed threshold flags |
| fifo with dynamic flags | Standard FIFO with runtime-configurable almost-full/empty flags |
| fifo with static flags | Standard FIFO with compile-time fixed status flags for area efficiency |
| multi req fifo with dynamic flags | Multi-request FIFO with programmable flags for high-throughput applications |
| multi req fifo with static flags | Multi-request FIFO with fixed flags for burst data buffering |
Memory FIFO Controllers
| Component | Description |
|---|---|
| asymmetric ctl fifo with dynamic flags | Asymmetric FIFO controller with runtime-configurable flags for external memory |
| asymmetric ctl fifo with static flags | Asymmetric FIFO controller with fixed flags for optimized control logic |
| ctl fifo with dynamic flags | Standard FIFO controller with programmable threshold flags |
| ctl fifo with static flags | Standard FIFO controller with compile-time fixed flags for area optimization |
| dual clock asymmetric ctl fifo with dynamic flags | Dual-clock asymmetric FIFO controller with programmable flags for CDC |
| dual clock asymmetric ctl fifo with static flags | Dual-clock asymmetric FIFO controller with fixed threshold flags |
| dual clock ctl fifo with dynamic flags | Dual-clock FIFO controller with runtime-configurable status flags |
| dual clock ctl fifo with static flags | Dual-clock FIFO controller with fixed flags for simple cross-domain control |
| dual clock multi req ctl fifo with dynamic flags | Dual-clock multi-request FIFO controller with programmable flags |
| dual clock multi req ctl fifo with static flags | Dual-clock multi-request FIFO controller with fixed threshold flags |
| multi req ctl fifo with dynamic flags | Multi-request FIFO controller with programmable flags for burst operations |
| multi req ctl fifo with static flags | Multi-request FIFO controller with fixed flags for high-throughput buffering |
Memory Registers
| Component | Description |
|---|---|
| pipeline register | Parameterized pipeline register for datapath staging |
| pipeline register with en | Pipeline register with enable control for clock gating and stall support |
| register with value reset | Register with configurable reset value for initialization |
| shadow register | Dual-bank register for atomic updates and configuration shadowing |
| shift register | Configurable shift register for serial-to-parallel conversion and delays |
Memory Stacks
| Component | Description |
|---|---|
| stack | Parameterized LIFO stack with configurable depth and width |
| stack ctl | Stack controller with push/pop operations and overflow/underflow detection |
Shifters Logic
| Component | Description |
|---|---|
| arithmetic left shifter | Arithmetic left shifter preserving sign bit for multiplication |
| arithmetic left tc shifter | Two's complement arithmetic left shifter for signed multiplication |
| arithmetic right shifter | Arithmetic right shifter with sign extension for division |
| arithmetic right tc shifter | Two's complement arithmetic right shifter for signed division |
| cyclic left shifter | Rotate left (barrel shifter) for circular bit manipulation |
| cyclic left tc shifter | Two's complement aware cyclic left shifter for signed rotation |
| cyclic right shifter | Rotate right with configurable shift amount |
| cyclic right tc shifter | Two's complement aware cyclic right shifter for signed rotation |
| left shifter | Logical left shifter with variable shift amount |
| left shifter with sticky | Left shifter with sticky bit for rounding support |
| left tc shifter | Two's complement aware left shifter for signed arithmetic |
| right shifter | Logical right shifter for division and bit field extraction |
| right shifter with sticky | Right shifter with sticky bit detection for precision control |
| right tc shifter | Two's complement right shifter maintaining numerical correctness |
SRAM
| Component | Description |
|---|---|
| array1rdwr dff | Single-port SRAM with DFF-based storage for read/write operations |
| array1rdwr latch | Single-port SRAM using latch-based memory for area efficiency |
| array1rd1wr dff | True dual-port SRAM with separate read and write ports (DFF) |
| array1rd1wr latch | True dual-port SRAM with latch-based implementation |
| array2rd1wr dff | Two-read one-write port SRAM for multi-access scenarios |
| array2rd1wr latch | Dual-read single-write SRAM with latch storage |
| arrayXrdXwr dff | Multi-port SRAM with configurable number of read and write ports (DFF) |
| arrayXrdXwr latch | Multi-port latch-based SRAM for maximum flexibility |
| arrayXrdXwr priority wr dff | Multi-port SRAM with priority-based write arbitration |
| arrayXrdXwr priority wr latch | Latch-based multi-port SRAM with write priority resolution |